According to Qbit News on November 6, domestic AI chip companyMotivehas closed two funding rounds within five months—each nearing RMB 1 billion. The company focuses exclusively on sparse-inference–dedicated chips.
Why has capital suddenly issued two checks for the word “sparse”? Because the large-model cost structure has shifted—computing demand has pivoted from training to inference, and inference is precisely where sparse computation excels.
DeepSeek of 3%: one figure explains the entire赛道
Qbit News offers an intuitive example: take DeepSeek-V4-Pro, which has roughly 1.6 trillion total parameters, yet activates only about 49 billion parameters per token,approximately 3% of its total parameter count..
This is the core trait of MoE (Mixture of Experts) architecture: the model is huge, but only a small subset of experts is activated for each task. In theory, 97% of the computation can be skipped. The problem lies in general-purpose GPUs, which strike compromises across diverse workloads—including training, inference, and scientific computing—and thus struggle with deep hardware-software co-optimization tailored to any specific sparsity pattern—the skipped computation doesn’t necessarily translate into real-world efficiency gains.
This is exactly where dedicated chips enter: if a chip’s compute units and data pathways are architected from day one around sparsity, that 3% activation rate could genuinely deliver nearly a 30× cost advantage—not just a theoretical headline number. As we noted in DeepSeek V4 Pro 0813 in-depth review , MoE sparse activation is one foundational reason why pricing for this generation of models has been driven down to such levels.
Who is Motive?
- Founded in 2018,Motive has focused solely on sparse computing since day one, pioneering the “weight sparsification + activation sparsification” dual-sparse algorithm and building full-stack solutions—including algorithms, compilers, chip architecture, and software toolchains—around it.
- Founding TeamHailing from Carnegie Mellon University and semiconductor companies including Intel, Qualcomm, and Marvell, the team officially claims production experience spanning dozens of products and over 5 billion chips shipped.
- MLPerf Inference During testing, the S30 accelerator card secured first place for three consecutive editions in several categories it participated in, with primary metrics being energy efficiency and per-unit-compute inference throughput.
- Inference ClustersAlready deployed across four major regions—Northwest, Southwest, East China, and North China—with revenue projected to grow several-fold in Q3 2026.
- Software StackThe upgraded SECA (Sparse-Native Efficient Computing Architecture) is imminent, focusing on large-model inference deployment and cluster operations to lower model migration barriers.
Two Real-World Deployment Cases: Offshore Computing Power and Remote Sensing Imagery
The first case vividly illustrates domestic computing power’s practical constraints. Mounchip participated in Shanghai’s state-owned asset platform–led project—the nation’s first “Offshore Computing Power Token Factory”—leveraging offshore wind power and seawater cooling to reduce PUE and electricity costs. Yet a paradox arises: if inference still runs on general-purpose GPUs, savings on electricity may be fully offset by chip-level inference costs. Sparse architecture addresses this by cutting per-token cost at the chip level, enabling “green-power cost reduction” and “architectural cost reduction” to compound—not cancel each other out.
The second case is more technical: Mounchip partnered with the Institute of Earth and Space Technologies at Peking University’s Shanghai Lingang International Science and Innovation Center to port two leading international foundational models for remote sensing image intelligence analysis onto its own accelerator cards. The result isNear-zero loss in operational accuracy and no need for downstream task retraining,achieving up to 2.88× higher inference throughput and up to 7.64× model compression.
These figures validate one critical point: model-level sparsity can be truly translated into end-to-end efficiency via hardware-software co-design—a feat far harder—and more valuable—than benchmark scores alone.
What This Means for Ordinary Users
No immediate direct changes are visible in the short term, but the medium-term transmission path is clear: lower inference costs → lower API pricing → application layers supporting longer contexts and more Agent calls. This chain has already proven effective, as evidenced by the accelerating price cuts among domestic models this year,GLM 5.3,Qwen3.8 2.4T A95B,DeepSeek V4 Pro benefiting all stakeholders.
Another layer of significance lies in supply security.U.S. federal agencies comprehensively banned DeepSeek Going forward, domestic demand for “computing power autonomy” will only intensify. Sparse-specialized chips offer a path to bypass head-on competition with general-purpose GPUs—not competing on peak compute, but on per-token cost.
Risks must also be clearly stated.
The biggest risk for specialized chips is “betting on the wrong architecture.” Sparse inference advantages heavily depend on models continuing down the MoE path; if next-generation architectures shift away from current sparsity patterns, the advantage of specialized hardware may erode. By contrast, general-purpose GPUs offer greater architectural tolerance. Moreover, ecosystem remains a critical weakness: CUDA’s moat lies not in hardware, but in hundreds of thousands of developers and mature operator libraries. Mounchip’s push for the SECA software stack and its industry-academia-research alliance is fundamentally aimed at closing this gap.
By the way,DeepSeek We have also been doing similar things at the system level, such as open-sourcing the Super-agent dual-layer scheduling architecture,as well as Compute expansion following a $1.5-billion funding roundCost reduction is being pursued simultaneously on both software and hardware fronts—this direction is now firmly established.
Frequently Asked Questions (FAQ)
What does sparse computing mean?
It refers to scenarios where large portions of a model’s parameters or computation results are zero (or insignificant), allowing those computations to be skipped. In MoE architectures, only a subset of experts is activated per inference step—a classic example of activation sparsity. Sparse computing hardware identifies and skips these ineffective computations, thereby reducing compute and data movement overhead.
Are Mounriver and Nvidia competitors?
They compete in inference scenarios, but not across the board. General-purpose GPUs handle training, inference, and scientific computing; Mounriver focuses exclusively on sparse inference, pursuing an “extreme specialization” strategy. Its target is not training accelerators, but rather the portion of datacenter compute dedicated to inference.
Will sparse chips make large-model APIs cheaper?
Directionally, yes. Inference cost constitutes the primary component of API pricing, and lower per-token hardware costs will gradually translate into lower prices. However, this translation lags and depends on actual chip shipment volumes and software ecosystem maturity—it won’t appear on bills immediately.
Why are MoE models especially well-suited for sparse chips?
Because MoE sparsity is structured and predictable—the router explicitly indicates which experts to activate for each inference step. Compared to unstructured sparsity (where zeros are scattered across matrices), structured sparsity enables more effective compiler- and hardware-level optimizations, yielding more consistent performance gains.
Summarize
Two rounds of financing totaling nearly RMB 1 billion signal investor recognition that the “sparse inference” technical path has entered its window of opportunity. Yet whether it can become China’s second pillar of domestic compute hinges on two less glamorous factors: whether the software ecosystem can retain developers, and whether next-generation model architectures continue favoring sparsity.
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